An embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same.
Recently, as the data storage capacity of semiconductor memory devices has increased and the integration level has also increased, the size of each unit cell has been required to become smaller. As the integration of the semiconductor device becomes higher, a distance between a gate and a bit line connected to a cell transistor becomes closer. As a result, parasitic capacitance increases to a decrease in the operating reliability of the semiconductor device. In order to improve the reliability of the semiconductor device, a buried-type gate structure has been suggested. In the buried-type gate structure, a conductive material is formed in a recess formed in a semiconductor substrate, and the upper portion of the conductive material is covered with an insulating film so that a gate may be buried in the semiconductor substrate. As a result, electric separation between a bit line and a bit line contact plug formed on the semiconductor substrate is more clearly defined. A semiconductor device comprising of the buried-type gate and a method for manufacturing the same are described as follows.
FIG. 1 is a layout diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, a semiconductor device includes a cell region I and a peripheral region II. In a cell region I, a device isolation structure 13 that defines an active region 15 is formed, and a plurality of gates 25 and a plurality of bit lines (not shown) are formed. The gate 25 is a buried gate, and a bit line contact plug 30 is formed on the active region 15 between the gates 25. The bit line (not shown) that contacts with the bit line contact plug 30 is formed perpendicular to the gate 25.
FIGS. 2a and 2b are cross-sectional diagrams illustrating the conventional semiconductor device and a method for manufacturing the same, which show cross-sectional views taken along a-a′ of FIG. 1.
Referring to FIG. 2a, a semiconductor substrate 10 including the cell region I and the peripheral region II is etched to form a trench for device isolation that defines the active region 15. The trench (not shown) is filled with an oxide film to form the device isolation structure 13. One integrated device isolation structure 13 is formed in a boundary section between the cell region I and the peripheral region II. The device isolation structure 13 and the active region 15 of the cell region I are etched to form a recess. A gate oxide film (not shown) and a barrier metal layer (not shown) are formed on the resultant surface including the recess. The barrier metal layer (not shown) includes a titanium nitride (TiN) film. A conductive material 20 is buried in the lower portion of the recess having the barrier metal layer (not shown). The conductive material 20 includes tungsten. A first sealing nitride film 23 is formed on the resultant structure including the recess filled with the conductive material 20 to form a buried-type gate 25.
Referring to FIG. 2b, the first sealing nitride film 23 is etched to form a bit line contact hole, and the bit line contact hole is filled with a conductive material to form a bit line contact plug 30. A second sealing nitride film 35 is formed on the resultant structure including the bit line contact plug 30. A mask pattern (not shown) that opens the peripheral region II is formed on the upper portion of the second sealing nitride film 35. The first sealing nitride film 23 and the second sealing nitride film 35 of the peripheral region II are removed using the mask pattern as a mask.
A gate oxidation process for forming a gate is performed on the peripheral region II to form a gate oxide film 40. The mask pattern (not shown) is removed. A process for forming a bit line is performed on the cell region I, and a process for forming a gate is performed on the peripheral region II.
Since the gate oxidation process is performed on the peripheral region II after the buried-type gate 25 is formed in the cell region I, oxygen ions generated from the oxidation process may move along an oxidation path as shown by path ‘A’ in FIG. 2b. As a result, the TiN film which is a barrier metal layer (not shown) of the buried-type gate 25 is oxidized. The oxidation of the barrier metal layer causes a gate oxide integrity (GOI) fail and an unlimited sensing delay (USD) fail.
In order to prevent the GOI fail and the USD fail, an overlap between the buried-type gate and the peripheral circuit open mask of the cell region requires an overlap of at least 640 nm or more, and a distance between the gates of the peripheral region of the open mask requires a space of at least 740 nm or more. A distance between the buried-type gate of the cell region and the gate of the peripheral region requires a space of at least 1380 nm or more. However, as the minimum distance between the cell region and the peripheral region increases, the size of a die also increases, which results in a decrease in the number of dies per wafer, thereby reducing the cost efficiency.